Consider 5 Stage Single Issued Pipelined Mips Datapath Consisting Instruction Fetch Instru Q30539525

Consider the 5-stage single-issued pipelined MIPS datapathconsisting of Instruction Fetch (IF),
Instruction Decode (ID), Execution (EX), Memory (MEM), andWrite-Back (WB). (10 points)
You are given the following MIPS instruction sequence:
# $s0 to $s3 = 56, 30, 30, 7
# $t0 to $t4 = 7, 7, 7, 7, 7
add $t0, $s0, $0
and $t1, $t0, $s1
or $t2, $t0, $s2
sub $t3, $t0, $s3
srl $t4, $t0, 2
Start numbering the cycles with 1 when the add instruction entersthe IF stage.
For part i. to iii. assume that the datapath is broken and there isno forwarding and no stalling.

i. What are the values of $t0 to $t4 at the end of cycle 7? (2points)
(a) 56, 24, 62, 7, 7
(b) 56, 24, 62, 49, 7
(c) 56, 6, 31, 7, 7
(d) 56, 6, 7, 7, 7
(e) None of the above
ii. What are the values of $t0 to $t4 at the end of cycle 8? (2points)
(a) 56, 24, 62, 49, 7
(b) 56, 24, 62, 49, 14
(c) 56, 6, 31, 49, 7
(d) 56, 6, 31, 7, 7
(e) None of the above

iii. What are the values of $t0 to $t4 at the end of cycle 9? (2points)
(a) 56, 24, 62, 49, 7
(b) 56, 24, 62, 49, 14
(c) 56, 6, 31, 49, 14
(d) 56, 6, 31, 0, 7
(e) None of the above
iv. What instruction(s) is/are computing the wrong result(s)(choose the answer that includes ALL
faulty instructions)? (2 points)
(a) add
(b) and, or
(c) and, or, sub
(d) and, or, sub, srl
(e) add, and, or, sub, srl

v. Say we want to completely fix the problem from part iv. usingforwarding. Which forwarding
path(s) do we need to provide in order to execute the code sequencecorrectly (it is implied that
multiplexers are inserted to join the forwarded signals with theoriginal signals)? (2 points)
(a) Output of ALU in the EX stage back to the input of the ALU inthe EX stage.
(b) Output of ALU in the MEM stage back to the output of RegisterFile in the ID stage.
(c) Output of ALU in the MEM stage back to the input of ALU in theEX stage.
(d) Both (a) and (b).
(e) Both (a) and (c).